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국제전문학술지

Variability study of Si nanowire FETs with different junction gradients, AIP advances, , 6, – (2016)

Effects of single grain boundary and random interface traps on electrical variations of sub-30 nm polysilicon nanowire structures, MICROELECTRONIC ENGINEERING, , 149, 113-116 (2016)

Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors, APPLIED PHYSICS LETTERS, , 106, – (2015)

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node, IEEE ELECTRON DEVICE LETTERS, , 36, 994-996 (2015)

Three-dimensional simulation of threshold voltage variations due to an oblique single grain boundary in sub-40nm polysilicon nanowire FETs, SEMICONDUCTOR SCIENCE AND TECHNOLOGY, , 30, – (2015)

Chemical Gated Field Effect Transistor by Hybrid Integration of One-Dimensional Silicon Nanowire and Two-Dimensional Tin Oxide Thin Film for Low Power Gas Sensor, ACS APPLIED MATERIALS & INTERFACES, , 7, 21263-21269 (2015)

Investigation of RC Parasitics Considering Middle-of-the-Line in Si-Bulk FinFETs for Sub-14-nm Node Logic Applications, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 62, 3441-3444 (2015)

High efficiency silicon solar cell based on asymmetric nanowire, SCIENTIFIC REPORTS, , 5, – (2015)

Silicon Nanowire Biologically Sensitive Field Effect Transistors: Electrical Characteristics and Applications, Journal of Nanoscience and Nanotechnology, , 14, 273-287 (2014)

Optimized operation of silicon nanowire field effect transistor sensors, NANOTECHNOLOGY, , 25, – (2014)

Threshold Voltage Variations Due to Oblique Single Grain Boundary in Sub-50-nm Polysilicon Channel, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 61, 2705-2710 (2014)

Single-crystalline CdTe nanowire field effect transistors as nanowire-based photodetector, PHYSICAL CHEMISTRY CHEMICAL PHYSICS, , 16, 22687-22693 (2014)

Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths, APPLIED PHYSICS LETTERS, , 105, – (2014)

Thermally Phase-Transformed In2Se3 Nanowires for Highly Sensitive Photodetectors, SMALL, , 10, 3795-3802 (2014)

Investigation of Low-Frequency Noise in p-type Nanowire FETs: Effect of Switched Biasing Condition and Embedded SiGe Layer, IEEE ELECTRON DEVICE LETTERS, , 35, 702-704 (2014)

Universal relaxation characteristic of interface trap under FN and NBTI stress in pMOSFET device, ELECTRONICS LETTERS, , 50, 1877-U245 (2014)

Improved performance of In2Se3 nanowire phase-change memory with SiO2 passivation, Solid-State Electronics, , 80, – (2013)

Analytic Model of S/D Series Resistance in Trigate FinFETs with Polygonal Epitaxy, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 60, 1302-1309 (2013)

Investigation of the electrical stability of Si-nanowire biologically sensitive field-effect transistors with embedded Ag/AgCl pseudo reference electrode, RSC Advances, , 3, 7963-7969 (2013)

Simple Source/Drain Series Resistance Extraction Method Optimized for Nanowire, IEEE ELECTRON DEVICE LETTERS, , 34, 828-830 (2013)

Improved Electrical Characteristics of Honeycomb-Nanowire ISFETs, IEEE ELECTRON DEVICE LETTERS, , 34, 1059-1061 (2013)

Study on a Scaling Length Model for Tapered Tri-gate FinFET based on 3-D Simulation and Analytical Analysis, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 60, 2721-2727 (2013)

Investigation of electromigration in In2Se3 nanowire for phase change memory devices, APPLIED PHYSICS LETTERS, , 103, – (2013)

Electrical characteristics of 20-nm junctionless Si nanowire transistors, Solid-State Electronics, , 73, – (2012)

Optical and electrical characteristics of asymmetric nanowire solar cells, JOURNAL OF APPLIED PHYSICS, , 111, – (2012)

Characteristics of gate-all-around silicon nanowire field effect transistors with asymmetric channel width and source/drain doping concentration, JOURNAL OF APPLIED PHYSICS, , 112, – (2012)

Device Design Guidelines for Nanoscale FinFETs in RF/Analog Applications, IEEE ELECTRON DEVICE LETTERS, , 33, 1234-1236 (2012)

Characterization of Channel Diameter Dependent Low Frequency Noise in Silicon Nanowire Field Effect Transistors, IEEE ELECTRON DEVICE LETTERS, , 33, 1348-1350 (2012)

Characterization and Modeling of 1/f Noise in Si-nanowire FETs _ Effects of Cylindrical Geometry and Different Processing of Oxides, IEEE TRANSACTIONS ON NANOTECHNOLOGY, , 10, 417-423 (2011)

C-V Characteristics in Undoped Gate-All-Around Nanowire FET Array, IEEE ELECTRON DEVICE LETTERS, , 32, 116-118 (2011)

An Analysis of the Field Dependence of Interface Trap Generation under Negative Bias Temperature Instability Stress using Wentzel- Kramers Brillouin with Density Gradient Method, Japanese Journal of Applied Physics, , 50, – (2011)

A 3-D Statistical Simulation Study of Mobility Fluctuations in MOSFET Induced by Discrete Trapped Charges in SiO2 Layer, IEEE TRANSACTIONS ON NANOTECHNOLOGY, , 10, 699-705 (2011)

Interfacial-Layer-Driven Dielectric Degradation and Breakdown of HfSiON/SiON Gate Dielectric nMOSFETs, IEEE ELECTRON DEVICE LETTERS, , 32, 1319-1321 (2011)

Silicon nanowire ion sensitive field effect transistor with integrated Ag/AgCl electrode: pH sensing and noise characteristics, Analyst, , 136, 5012-5016 (2011)

Comprehensive Study of Quasi-Ballistic Transport in High-k/Metal Gate nMOSFETs, IEEE ELECTRON DEVICE LETTERS, , 32, 1474-1476 (2011)

New Investigation of Hot Carrier Degradation on RF Small-Signal Parameter and Performance in High-k/Metal Gate nMOSFETs, IEEE ELECTRON DEVICE LETTERS, , 32, 1668-1670 (2011)

Characteristics of the Series Resistance Extracted from Si-Nanowire FETs using the Y-function Technique, IEEE TRANSACTIONS ON NANOTECHNOLOGY, , 9, 212-217 (2010)

Comparison of Series Resistance and Mobility Degradation Extracted from n- and p-type Si-NWFETs Using the Y-function Technique, JAPANESE JOURNAL OF APPLIED PHYSICS, , 49, – (2010)

Characterization of Near-Interface Oxide Trap Density in Nitrided Oxides for Nano-Scale MOSFET Applications, IEEE TRANSACTIONS ON NANOTECHNOLOGY, , 8, 654-658 (2009)

A Comparative Study of the DRAM Leakage Mechanism for Planar and Recessed Channel MOSFETs, SOLID-STATE ELECTRONICS, , 53, 998-1000 (2009)

Three-dimensional Simulation of Dopant Fluctuation Induced Threshold Voltage Dispersion in Non-planar MOS Structures Targeting Flash EEPROM Transistors, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 55, 1456-1463 (2008)

A Proposal on an Optimized Device Structure With Experimental Studies on Recent Devices for the DRAM Cell Transistor, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 54, 3325-3335 (2007)

Edge Profile Effect of Tunnel Oxide on Erase Threshold Voltage Distributions in Flash Memory Cells, IEEE TRANSACTIONS ON ELECTRON DEVICES, , 53, 3012-3019 (2006)

Reliable Extraction of Cycling Induced Interface States Implementing Realistic P/E Stresses in Reference Cell: Comparison with Flash Memory Cell, IEEE ELECTRON DEVICE LETTERS, , 27, 169-171 (2006)

Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells, JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, , 44, L578-L580 (2005)

Simple Experimental Determination of the Spread of Trapped Hot Holes Injected in Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Cells: Optimized Erase and Cell Shrinkage, JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, , 43, L1611-L1613 (2004)

Spatial and Temporal Characterization of Programming Charge in SONOS Memory Cell: Effects of Localized Electron Trapping, JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS, , 43, L1581-L1583 (2004)

High Speed, Low Power Programming in 0.17mum Channel Length NOR-type Floating Gate Flash Memory Cell Free of Drain Turn-On Effects, JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS, , 43, L224-L226 (2004)

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